A Noise-tolerant Match-line Scheme for Low-power and High-speed Content-addressable Memory

A novel NOR-type match-line scheme with XOR-based conditional keeper for content-addressable memory (CAM) is presented in this paper. High fan-in NOR-type match-line circuits require robust keepers to resist onchip noises. The XOR-based conditional keeper is turned off at some critical moments to reduce the delay and power consumption. The timing of control signals and their effects on noise immunity, power and delay are also examined. High fan-in NOR-type match-line schemes are used to demonstrate the effectiveness of the XORbased conditional keeper on noise immunity. All the simulation results are based on TSMC 100nm CMOS technology. Compared to conventional techniques, under the same unity-gain DC noise criteria, more than 20% delay reduction, 19% power reduction and 35% energy saving are achieved. The area overhead of 64-bit CAM word scheme is 1.45%.